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Data Processing Unit
Results: 324

#	Item
301	COVER FEATURE Scaling to the End of Add to Reading List Source URL: www.cs.utexas.edu Language: English - Date: 2005-07-18 11:41:20 Central processing unit Parallel computing Microprocessors Classes of computers Explicit Data Graph Execution Microarchitecture Superscalar Instruction set TRIPS architecture Computer architecture Computing Computer engineering
302	x86-64 Machine-Level Programming∗ Randal E. Bryant David R. O’Hallaron Add to Reading List Source URL: www.cs.cmu.edu Language: English - Date: 2005-09-11 16:57:44 X86 architecture Assembly languages Central processing unit Data types X86 assembly language X86-64 X86 MOV 64-bit Computer architecture Computing Instruction set architectures
303	Appears in the ¿ Ø Annual International Symposium on Microarchitecture Distributed Microarchitectural Protocols in the TRIPS Prototype Processor Add to Reading List Source URL: www.cs.utexas.edu Language: English - Date: 2006-10-26 23:09:43 Central processing unit Microprocessors Alpha 21264 CPU cache Microarchitecture Explicit Data Graph Execution Superscalar Branch predictor AMD 10h Computer architecture Computer hardware Computer engineering
304	An Empirical Study of Data Speculation Use on the Intel Itanium 2 Processor Markus Mock Add to Reading List Source URL: www.info.uni-karlsruhe.de Language: English - Date: 2005-07-01 08:51:12 Programming language implementation Advanced load address table Instruction set architectures Itanium Explicitly parallel instruction computing Speculative execution ALAT Instruction-level parallelism Processor register Computer architecture Computer hardware Central processing unit
305	House for the History of IBM Data Processing Hollerith Electric Tabulating System[removed] Add to Reading List Source URL: www-03.ibm.com Language: English - Date: 2009-04-13 22:15:24 Computer hardware Punched card Dehomag Tabulating machine Herman Hollerith Punched card input/output IBM Time clock Keypunch Computing Technology Unit record equipment
306	The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA Add to Reading List Source URL: www.eecs.berkeley.edu Language: English - Date: 2011-05-13 18:42:11 X86 Addressing mode Instruction set Reduced instruction set computing ARM architecture 64-bit Data structure alignment Microcode Central processing unit Computer architecture Computing Instruction set architectures
307	User Commands DINEROIV ( 1 ) Add to Reading List Source URL: www.cc.gatech.edu Language: English - Date: 2002-11-01 11:29:22 Computer hardware CPU cache Central processing unit Compiler construction Data Data structure alignment Dinero Endianness Cache Computer memory Computing
308	PDF Document Add to Reading List Source URL: www.vldb.org Language: English - Date: 2006-07-29 01:39:22 Data Database management systems Cache CPU cache Central processing unit Computer memory Relational database PaX Tar Data management Computing Database theory
309	PDF Document Add to Reading List Source URL: www.jilp.org Language: English - Date: 2002-06-10 14:05:11 Computer programming Parallel computing Central processing unit Non-blocking algorithm Synchronization Thread Lock CPU cache Data parallelism Computing Concurrent computing Concurrency control
310	PDF Document Add to Reading List Source URL: www.jilp.org Language: English - Date: 2004-01-21 11:48:44 Computer architecture Central processing unit Instruction-level parallelism Data parallelism Microarchitecture Java bytecode Task parallelism Superscalar Thread Computing Computer programming Parallel computing

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